A Low-Power Capacitive Charge Pump Based Pipelined ADC

被引：54

作者：

Ahmed, Imran ^{[1
]}

Mulder, Jan ^{[2
]}

Johns, David A. ^{[1
]}

机构：

[1] Univ Toronto, Dept Elect & Comp Engn, Toronto, ON M5S 3G4, Canada

[2] Broadcom Netherlands, Bunnik, Netherlands

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2010年 / 45卷 / 05期

基金：

加拿大自然科学与工程研究理事会;

关键词：

ADC; charge pump; CMOS; common-mode-feedback; foreground calibration; linear sampling; low-power; opampless; pipelined; 10-BIT; CMOS; CIRCUITS; OPAMP;

D O I：

10.1109/JSSC.2010.2042524

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A low-power pipelined ADC topology is presented which uses capacitive charge pumps, source-followers, and digital calibration to eliminate the need for power-hungry opamps to achieve good linearity in a pipelined ADC. The differential charge pump technique achieves 10-bit linearity, and does not require an explicit common-mode-feedback circuit. The ADC was designed to operate at 50 MS/s in a 1.8 V, 0.18 mu m CMOS process, where measured results show the peak SNDR and SFDR of the ADC to be 58.2 dB (9.4 ENOB), and 66 dB respectively. The ADC consumes 3.9 mW for all active circuitry and 6 mW for all clocking and digital circuits.

引用

页码：1016 / 1027

页数：12

共 43 条

[1] A 50-MS/s (35 mW) to 1-kS/s (15 μW) power scaleable 10-bit pipelined ADC using rapid power-on opamps and minimal bias current variation [J].

Ahmed, I ;

Johns, DA .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2005, 40 (12) :2446-2455

[2]

AHMED I, 2009, IEEE INT SOL STAT A, V165, P164

[3] A high bandwidth power scalable sub-sampling 10-bit pipelined ADC with embedded sample and hold [J].

Ahmed, Imran ;

Johns, David A. .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2008, 43 (07) :1638-1647

[4] Low-power pipeline ADC for wireless LANs [J].

Arias, J ;

Boccuzzi, V ;

Quintanilla, L ;

Enríquez, L ;

Bisbal, D ;

Banu, M ;

Barbolla, J .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2004, 39 (08) :1338-1340

[5]

BROOKS L, 2007, IEEE INT SOL STAT CI, P460

[6]

BROOKS L, 2009, IEEE INT SOL STAT A, V167, P166

[7] A 1.4-V 10-bit 25-MS/s pipelined ADC using opamp-reset switching technique [J].

Chang, DY ;

Moon, UK .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2003, 38 (08) :1401-1404

[8]

Choi H. C., 2006, IEEE INT SOL STAT CI, P842

[9] SWITCHED-OPAMP - AN APPROACH TO REALIZE FULL CMOS SWITCHED-CAPACITOR CIRCUITS AT VERY-LOW POWER-SUPPLY VOLTAGES [J].

CROLS, J ;

STEYAERT, M .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1994, 29 (08) :936-942

[10] ON-CHIP HIGH-VOLTAGE GENERATION IN MNOS INTEGRATED-CIRCUITS USING AN IMPROVED VOLTAGE MULTIPLIER TECHNIQUE [J].

DICKSON, JF .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1976, 11 (03) :374-378

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