Novel Eight-Transistor SRAM cell for write power reduction

被引：8

作者：

Prabhu, C. M. R. ^{[1
]}

Singh, Ajay Kumar ^{[1
]}

机构：

[1] Multimedia Univ, Fac Engn & Technol, Melaka 75450, Malaysia

来源：

IEICE ELECTRONICS EXPRESS | 2010年 / 7卷 / 16期

关键词：

low power; SRAM cell; write/read delay; write power; stability and static noise margin; CIRCUIT; MARGIN;

D O I：

10.1587/elex.7.1175

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents a novel 8T SRAM cell which contains two tail transistors in the pull-down path of the respective inverter to minimize the write power consumption. The simulated results show that the proposed cell consumes about 57.87% lower power and gives faster response compared to the conventional 6T SRAM cell during a write operation. To compensate the read delay and static noise margin (SNM) losses due to the two extra tail transistors in the proposed cell, we have to enlarge the width of these two tail transistors.

引用

页码：1175 / 1181

页数：7

共 12 条

[1] Low-power cache design using 7T SRAM cell [J].

Aly, Ramy E. ;

Bayoumi, Magdy A. .

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2007, 54 (04) :318-322

[2] The impact of intrinsic device fluctuations on CMOS SRAM cell stability [J].

Bhavnagarwala, AJ ;

Tang, XH ;

Meindl, JD .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2001, 36 (04) :658-665

[3]

CHANDRAKASAN A, 2000, DESIGN HIGH PERFORMA, P584

[4]

Chang YJ, 2004, IEEE T VLSI SYST, V12, P827, DOI [10.1109/TVLSI.2004.831471, 10.1109/tvlsi.2004.831471]

[5] Read stability and write-ability analysis of SRAM cells for nanometer technologies [J].

Grossar, Evelyn ;

Stucchi, Michele ;

Maex, Karen ;

Dehaene, Wim .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2006, 41 (11) :2577-2588

[6] Low-power logic circuit and SRAM cell applications with silicon on depletion layer CMOs (SODEL CMOS) technology [J].

Inaba, Satoshi ;

Nagano, Hajime ;

Miyano, Kiyotaka ;

Mizushima, Ichiro ;

Okayama, Yasunori ;

Nakauchi, Takahiro ;

Ishimaru, Kazunari ;

Ishiuchi, Hidemi .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2006, 41 (06) :1455-1462

[7] Quantitative analysis and optimization techniques for on-chip cache leakage power [J].

Kim, NS ;

Blaauw, D ;

Mudge, T .

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2005, 13 (10) :1147-1156

[8] Characterization of a novel nine-transistor SRAM cell [J].

Liu, Zhiyu ;

Kursun, Volkan .

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2008, 16 (04) :488-492

[9] STATIC-NOISE MARGIN ANALYSIS OF MOS SRAM CELLS [J].

SEEVINCK, E ;

LIST, FJ ;

LOHSTROH, J .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1987, 22 (05) :748-754

[10] Power deduction in digital signal processing circuit using inventive CPL subtractor circuit [J].

Senthilpari, C. ;

Diwakar, K. ;

Prabhu, C. M. R. ;

Singh, Ajay Kumar .

2006 IEEE INTERNATIONAL CONFERENCE ON SEMICONDUCTOR ELECTRONICS, PROCEEDINGS, 2006, :820-+

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