Simulation in low-power embedded processor design

A low-power architecture and a simulation environment for its power consumption are proposed dedicatedly for embedded processors. The low-power consumption of the embedded processor can be achieved by means of an object code compression approach. This approach unifies duplicated instructions existing in an embedded program and assigns a compressed object code to such an instruction. An instruction decompresser is constructed so as to generate an object code from each compressed object code (pseudo code) input. A single-chip implementation of this decompresser together with a processor core can effectively reduce the bandwidth required for the I/O interface. To demonstrate the practicability of the proposed approach, a number of simulations are experimentally applied to an embedded processor ARM610, which attain 62.5% code compression, and hence 42.3% of the power consumption of instruction memory can be reduced.