Stress minimization in deep sub-micron full CMOS devices by using an optimized combination of the trench filling CVD oxides

被引：26

作者：

Park, MH ^{[1
]}

Hong, SH ^{[1
]}

Hong, SJ ^{[1
]}

Park, T ^{[1
]}

Song, S ^{[1
]}

Park, JH ^{[1
]}

Kim, HS ^{[1
]}

Shin, YG ^{[1
]}

Kang, HK ^{[1
]}

Lee, MY ^{[1
]}

机构：

[1] Samsung Elect Co Ltd, Semicond R&D Ctr, Kyonggi Do 449900, South Korea

来源：

INTERNATIONAL ELECTRON DEVICES MEETING - 1997, TECHNICAL DIGEST | 1997年

关键词：

D O I：

10.1109/IEDM.1997.650472

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We have found that the defect generation which is reduced by the mechanical stress during the densification, depends on the ratio of the trench filling material composed of the TEOS-O-3 based CVD oxide with tensile stress and the plasma enhanced CVD oxide with compressive stress. The lower as-deposited stress on the lower the maximun stress during the densification is. This stress level is proportional to the defect density which is generated by fabricating MOSFETs with Shallow Trench Isolation (STI). In order to achieve devices without a defect, it is important to minimize as-deposited stress level by optimizing the ratio of the trench filling CVD oxides.

引用

页码：669 / 672

页数：4