Failure Analysis Case Studies on Wafer Edge Failure due to Process Uniformity Issue

被引：0

作者：

Xu, N. Y. ^{[1
]}

Ng, H. P. ^{[1
]}

Ang, G. B. ^{[1
]}

Chen, C. Q. ^{[1
]}

Teo, A. ^{[1
]}

Jerome, A. ^{[1
]}

Tam, Y. S. ^{[1
]}

Li, Y. ^{[1
]}

Mai, Z. H. ^{[1
]}

机构：

[1] GLOBALFOUNDRIES Singapore, PTF Dept, Prod Failure Anal Grp, Singapore, Singapore

来源：

2018 25TH IEEE INTERNATIONAL SYMPOSIUM ON THE PHYSICAL AND FAILURE ANALYSIS OF INTEGRATED CIRCUITS (IPFA) | 2018年

关键词：

Wafer edge; Yield loss; Process uniformity; Etching; CMP; Lithography; Case strudies;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In modern foundry industry, capacity and yield are the two very important indicators to show how good the foundry is. In the past decades, the size of silicon wafer has been increased from 100nm to current 300nm, so that more dies can be packed the wafer. However, due to process constrains and increasing in the wafer dimension, the yield loss on wafer edge becomes more severe. Failure analysis acts as a powerful tool to help Fab in identifying the root cause of the wafer edge failure. In this paper, several wafer edge cases caused by different process modules were presented. The FA findings provided the evidence to show how the process uniformity limitation can cause the failure on wafer edge. Hence, Fab can take the corresponding actions to solve the issue, also continuously process tuning activities can be carried out, hence the yield loss on wafer edge can be reduced.

引用

页数：5