Effect of Ground Plane Design for WLP with Signal Integrity Modeling and Analysis

被引：0

作者：

Siew, Glen ^{[1
]}

Yan, Tee Tong ^{[1
]}

Chen Haoyang ^{[1
]}

Soh, Serine ^{[1
]}

Heon, Kim Jong ^{[1
]}

机构：

[1] Nepes Pte Ltd, R&D Team, 12,Ang Mo Kio St 65, Singapore 569060, Singapore

来源：

2010 IEEE ELECTRICAL DESIGN OF ADVANCED PACKAGE & SYSTEMS SYMPOSIUM | 2010年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Analysis of ground plane design effect for Wafer Level Package (WLP) through advance electrical modeling and simulation for chip-package-board signal integrity co-design was carried out. Increase in information transfer rates is greatly limited by bandwidth of communication channel at PCB board receiver due to channel loss, signal cross-talk, and signal distortion which are critical factors affecting signal integrity of channel and high-speed links such as LVDS, SSTL, LVTTL, LVCMOS and PCI-X. In this work, ground plane design approaches of 2 metal-layer WLP were studied to enhance the signal margin of high-speed signals.

引用

页数：4

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