3D Stacking By Hybrid Bonding with Low Temperature Solder

Three dimensional (3D) IC integration technologies have become essential as the market demands for product with low power consumption, multi functions, smaller size and faster response have been increasing. 3D stacking with conventional high melting temperature solders such as SnAg and Sn may induce high thermal stress to the package. In this paper, chip to chip 3D stacking using no flow underfill material and low temperature solder is demonstrated. The stacking of 100 mu m thin chips with 7mmx7mm size onto 350 mu m thin substrate with 10mmx10mm size at 100 mu m bump pitch was developed. Indium base solder was used to allow low temperature (< 200 degrees C) integration. Two types of underfill material were evaluated in terms of their shear strength and interfacial quality through C-SAM results before and after reliability test. Optimization of dispensing process parameters has been performed. The effect of bonding process parameters such as temperature, force and time on bonding strength has been analyzed by design of experiment (DOE) study and optimal bonding condition has been achieved. Quality of solder joints was assessed in terms of shear strength, microstructure and compositional observations of by means of X-Ray inspection, destructive shear test, cross-section analysis and scanning electron microscope (SEM).