An ultra-low power successive approximation A/D converter with time-domain comparator

被引：22

作者：

Agnes, Andrea ^{[1
]}

Bonizzoni, Edoardo ^{[1
]}

Malcovati, Piero ^{[2
]}

Maloberti, Franco ^{[1
]}

机构：

[1] Univ Pavia, Dept Elect, I-27100 Pavia, Italy

[2] Univ Pavia, Dept Elect Engn, I-27100 Pavia, Italy

来源：

ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING | 2010年 / 64卷 / 02期

关键词：

Analog-digital conversion; SAR; Low-power; ADC;

D O I：

10.1007/s10470-010-9466-8

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper presents an ultra-low power successive approximation analog-to-digital converter. An improved implementation of the binary weighted capacitors array and a novel comparator that operates in the time instead of the voltage domain are effective and power efficient. The circuit, fabricated in a conventional 0.18-mu m CMOS technology, achieves a sampling rate of 100 kS/s and an effective number of bit of 9.4. Using a 1-V supply voltage, the achieved power consumption is 3.8 mu W, leading to a Figure of Merit as low as 56 fJ/conversion-level.

引用

页码：183 / 190

页数：8

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