共 17 条
[1]
Aguirre M., 2005, P C NAS MIL AER PROG
[3]
Battezzati N., 2008, IND EL 2008 ISIE 200, P2282
[4]
A framework for reliability assessment and enhancement in multi-processor systems-on-chip
[J].
DFT 2007: 22ND IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT-TOLERANCE IN VLSI SYSTEMS, PROCEEDINGS,
2007,
:132-140
[5]
Bolchini C., 2007, P ACM IEEE GREAT LAK, P55
[6]
TMR and partial dynamic reconfiguration to mitigate SEU faults in FPGAs
[J].
DFT 2007: 22ND IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT-TOLERANCE IN VLSI SYSTEMS, PROCEEDINGS,
2007,
:87-95
[7]
Casini F., 2007, INT SYM DEFEC FAU TO, P105, DOI DOI 10.1109/DFT.2007.45
[9]
KENTERLIS P, 2006, IOLTS 06, P235
[10]
Soft error sensitivity characterization for microprocessor dependability enhancement strategy
[J].
INTERNATIONAL CONFERENCE ON DEPENDABLE SYSTEMS AND NETWORKS, PROCEEDINGS,
2002,
:416-425