A 3.3-V single power supply 16-Mb nonvolatile virtual DRAM using a NAND flash memory technology

A 3.3-V 16-Mb nonvolatile memory having operation virtually identical to DRAM with package pin compatibility has been developed, Read and write operations are fully DRAM compatible except for a longer RAS precharge time after write, Fast random access time of 63 ns with the NAND hash memory cell is achieved by using a hierarchical row decoder scheme and a unique folded bit-line architecture which also allows bit-by-bit program verify and inhibit operation, Fast page mode with a column address access time of 21 ns is achieved by sensing and latching 4k cells simultaneously, To allow byte alterability, non-volatile restore operation with self-contained erase is developed, Self-contained erase is word-line based, and increased cell disturb due to the word-line based erase is relaxed by adding a boosted bit-line scheme to a conventional self-boosting technique, The device is fabricated in a 0.5-mu m triple-well, p-substrate CMOS process using two-metal and three-poly interconnect layers, A resulting die size is 86.6 mm(2), and the effective cell size including the overhead of string select transistors is 2.0 mu m(2).