New paradigm of predictive MOSFET and interconnect modeling for early circuit simulation

被引：352

作者：

Cao, Y ^{[1
]}

Sato, T ^{[1
]}

Orshansky, M ^{[1
]}

Sylvester, D ^{[1
]}

Hu, CM ^{[1
]}

机构：

[1] Univ Calif Berkeley, Dept Elect Engn & Comp Sci, Berkeley, CA 94720 USA

来源：

PROCEEDINGS OF THE IEEE 2000 CUSTOM INTEGRATED CIRCUITS CONFERENCE | 2000年

关键词：

D O I：

10.1109/CICC.2000.852648

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A new paradigm of predictive MOSFET and interconnect modeling is introduced. This approach is developed to specifically address SPICE compatible parameters for future technology generations. For a given technology node, designers can use default values or directly input L-eff, T-ox, V-t, R-dsw and interconnect dimensions to instantly obtain a BSIM3v3 customized model for early stages of circuit design and research. Models for 0.18 mu m and 0.13 mu m technology nodes with L-eff down to 70nm are currently available on the web. Comparisons with published data and 2D simulations are used to verify this predictive technology model.

引用

页码：201 / 204

页数：4

共 11 条

[1] A high performance 0.25 mu m logic technology optimized for 1.8V operation [J].

Bohr, M ;

Ahmed, SS ;

Ahmed, SU ;

Bost, M ;

Ghani, T ;

Greason, J ;

Hainsey, R ;

Jan, C ;

Packan, P ;

Sivakumar, S ;

Thompson, S ;

Tsai, J ;

Yang, S .

IEDM - INTERNATIONAL ELECTRON DEVICES MEETING, TECHNICAL DIGEST 1996, 1996, :847-850

[2]

Cheng Y., 1996, BSIM3V3 MANUAL

[3]

IMAI K, 1999, S VLSI TECH, P51

[4]

MIYAMA M, P IEEE1999 CICC

[5]

ORSHANSKY M, UNPUB PREDICTION NEX

[6] Gate-work function engineering using poly-(Si,Ge) for high-performance 0.18μm CMOS technology [J].

Ponomarev, YV ;

Salm, C ;

Schmitz, J ;

Woerlee, PH ;

Stolk, PA ;

Gravesteijn, DJ .

INTERNATIONAL ELECTRON DEVICES MEETING - 1997, TECHNICAL DIGEST, 1997, :829-832

[7]

Rodder M, 1996, IEDM - INTERNATIONAL ELECTRON DEVICES MEETING, TECHNICAL DIGEST 1996, P563, DOI 10.1109/IEDM.1996.554046

[8]

SU L, 1998, S VLSI, P18

[9]

YANG IY, 1998, S VLSI TECHN, P148

[10] A high performance 180 nm generation logic technology [J].

Yang, S ;

Ahmed, S ;

Arcot, B ;

Arghavani, R ;

Bai, P ;

Chambers, S ;

Charvat, P ;

Cotner, R ;

Gasser, R ;

Ghani, T ;

Hussein, M ;

Jan, C ;

Kardas, C ;

Maiz, J ;

McGregor, F ;

McIntyre, B ;

Nguyen, P ;

Packan, P ;

Post, I ;

Sivakumar, S ;

Steigerwald, J ;

Taylor, M ;

Tufts, B ;

Tyagi, S ;

Bohr, M .

INTERNATIONAL ELECTRON DEVICES MEETING 1998 - TECHNICAL DIGEST, 1998, :197-200

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