High-level design flow for all-digital PLLs\

被引：1
|
作者：
Dondi, Silvia
Strandberg, Roland [1 ]
Nilsson, Magnus [1 ]
Boni, Andrea [1 ]
Andreani, Pietro [1 ]
机构：
[1] Univ Parma, Dipartimento Ingn Informaz, Vle GP Usberti 181-A, I-43100 Parma, Italy
来源：
24TH NORCHIP CONFERENCE, PROCEEDINGS | 2006年
关键词：
D O I：
10.1109/NORCHP.2006.329221
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
Deep-submicrometer CMOS processes are not suitable for traditional analog circuit design but they provide new opportunities of integrating complex digital functions. Within RF wireless communications, frequency synthesis stands out as a fundamental feature and novel digital solutions have been suggested for its implementation. Moving from an existing model, the goal of this paper is to outline the steps of a high-level approach to the design of an all-digital phase-locked loop (ADPLL).
引用
收藏
页码：247 / +
页数：2
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