Parallel Monitoring Architecture for 100 Gbps and Beyond Optical Ethernet

被引：0

作者：

Otsuki, Hideki ^{[1
]}

Kawai, Eiji ^{[1
]}

Setoyama, Katsuyoshi ^{[2
]}

Kimiyama, Hiroyuki ^{[3
]}

Sebayashi, Katsuhiro ^{[4
]}

Maruyama, Mitsuru ^{[4
]}

机构：

[1] Natl Inst Informat & Commun Technol, ICT Testbed Res & Dev Promot Ctr, Tokyo, Japan

[2] NTT Technocross, Media Innovat Div, Tokyo, Japan

[3] Daido Univ, Dept Informat Syst, Nagoya, Aichi, Japan

[4] Kanagawa Inst Technol, Dept Informat Network & Commun, Atsugi, Kanagawa, Japan

来源：

35TH INTERNATIONAL CONFERENCE ON INFORMATION NETWORKING (ICOIN 2021) | 2021年

关键词：

Ethernet; Monitoring; AWG; FPGA;

D O I：

暂无

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this study, we propose an architecture for monitoring packets coming from a high-speed optical Ethernet network. Moreover, we implement a packet monitoring system adopting our proposed architecture using general PC-based equipment with a field-programmable gate array (FPGA)based network interface card (NIC). We also experimentally achieve a full line-rate processing capability for 100-Gbps Ethernet and examine its feasibility on 400-Gbps Ethernet.

引用

页码：358 / 360

页数：3