A Theoretical Study on Porous-Silicon Based Synapse Design for Neural Hardware

Porous silicon (po-Si) is a form of silicon (Si) with nanopores of tunable sizes and shapes distributed over the bulk structure. Although crystalline Si (c-Si) is already established as one of the most advantageous and promising elements for its technological significance, the additional key aspect of po-Si is its large surface area with respect to its small volume which is beneficial for surface chemistry. In this work, we explore the design of a po-Si based synaptic device and investigate its potential for neuromorphic hardware. First, we analyze several electrical properties of po-Si through density functional theory (Ab Initio/ first principle) calculation. We show that the presence of intra-pore dangling states appears within the bandgap region of po-Si. While the bandgap of the po-Si is well known to be higher than c-Si yielding low carrier density and higher resistance, the appearance of these dangling states can significantly participate in electronic transport through hopping mechanism. Then, we analyze the electric-field driven modulation in the dangling bond through controlled infra-pore Si-H bond dissociation. Such modulation of the dangling state density further allows the tenability of the po-Si conductance. Finally, we theoretically evaluate the current-voltage characteristics of our proposed po-Si based synaptic devices and determine the possible range of obtainable conductivity for different porosity. Our analysis signifies that the integration of such devices in the synaptic fabric can enable significantly denser and energy-efficient neuromorphic hardware.