A high resolution flash time-to-digital converter taking into account process variability

Timing issues are a major concern -in the design of high performance synchronous, asynchronous circuits and GALS. Investigations into the causes of many timing problems cannot be satisfactorily undertaken using external equipment due to its remoteness from the source of the potential problem; this necessitates the development of on-chip time measurement circuitry. Current techniques have the capability of resolving timing differences down to 5ps [1], however further improvement is impeded by process variations. This paper describes a flash Time to Digital Converter (TDC) suitable for on-chip implementation. The theory to overcome the effects of process variations, potentially permitting the time resolution down to one picosecond is described. Proof of concept is demonstrated by implementing the techniques in an FPGA, improving on the current resolution of FPGA implementation of a TDC.