High-speed CMOS frequency divider

被引:12
作者
Chen, RY [1 ]
机构
[1] Nantai Inst Technol, Dept Elect Engn, Tainan 710, Taiwan
关键词
frequency dividers; CMOS integrated circuits;
D O I
10.1049/el:19971298
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A high-speed CMOS frequency divider is proposed. Using fewer transistors and only NMOS transistors in the regenerative circuits of the latches. the frequency divider achieves higher speed through the reduced capacitances at the output nodes and larger transconductance. A device sizing rule for the maximum input frequency is given. The proposed frequency divider is suitable for high-speed operation, while consuming a moderate amount of power.
引用
收藏
页码:1864 / 1865
页数:2
相关论文
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FUJISHIMA, M ;
ASADA, K ;
OMURA, Y ;
IZUMI, K .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1993, 28 (04) :510-512
[2]  
*UMC, 1995, NC7DAFB UMC
[3]  
Weste N. H. E., 1985, Principles of CMOS VLSI Design: A Systems Perspective