Ultra Low-Loss 50-70 GHz SPDT Switch in 90 nm CMOS

被引：0

作者：

Uzunkol, Mehmet ^{[1
]}

Rebeiz, Gabriel M. ^{[1
]}

机构：

[1] Univ Calif San Diego, San Diego, CA 92103 USA

来源：

2009 ANNUAL IEEE COMPOUND SEMICONDUCTOR INTEGRATED CIRCUIT SYMPOSIUM - 2009 IEEE CSIC SYMPOSIUM, TECHNICAL DIGEST 2009 | 2009年

关键词：

SPDT switch; millimeter-wave; 90-nm CMOS; BAND LOW-LOSS;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents an ultra low-loss 50-70 GHz single-pole double-throw (SPDT) switch built using standard 90 nm CMOS process. The switch is based on AM transmission lines with shunt inductors at the output matching network. High substrate resistance contacts are used to achieve low insertion loss. The SPDT switch results in a measured insertion loss of 1.5 dB at 55 GHz and <2 dB at 50-70 GHz. The measured isolation is > 25 dB, and the output port-to-port isolation is > 27 dB at 50-70 GHz. The measured P-1dB is 13.5 dBm with a corresponding IIP3 of 22.5 dBm at 60 GHz. The return loss is better than -8 dB at 50-70 GHz. The active chip area is 0.5x0.55 mm(2) and can be reduced in future designs by folding the on lambda/4 transmission lines. To our knowledge, this paper presents the lowest insertion loss 60 GHz SPDT in any CMOS technology to-date.

引用

页码：179 / 182

页数：4

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