TDevCGen: A Synthesis Toolset of HW/SW Communication Protocol Monitors from high-level Specifications

The use of an electronic embedded system for general or multi-purpose applications has increased substantially and while they require more flexibility for processing different types of applications and communication protocols. The need for this high flexibility also requires the use of general purpose processors as a solution for configuring and controlling a considerable amount of peripherals, what consequently implies in an increasing need for hardware-dependent software (HdS). HdS is a highly critical component and error prone due to the nature of the environment in which it is inserted, and it's hard coding. So it is essential to support the development and runtime phases of HdS by methodologies that are able to capture devices' accesses violations, through the monitoring of the communication protocol specification. So, this paper presents the toolset TDevCGen. This toolset synthesizes properties monitors, for checking hardware/software communication protocol, described through a high-level DSL called TDevC language. Before synthesizing the monitor model (SystemC or SystemVerilog) for runtime validation, the TDevCGen performs a sequence of validation in the specification input, looking for type mismatch, properties inconsistencies and the presence of nondeterministic in the specified protocol. Experiments using a DM9000A Ethernet device and an Altera UART show the efficiency and practicality of proposed approach (TDevCGen). The approach TDevCGen supports the specification of the protocol and communication properties, reducing the time of verification phase significantly, and performs a fast and reliable monitor's synthesis from a high-level specification, eliminating the use of general purpose languages, error-prone coding, and, thus, increasing the reliability of communication checking.