Multi-processor SoC integration: A case study on BlueGene/L

被引：0

作者：

Nsame, T ^{[1
]}

Savaria, Y ^{[1
]}

机构：

[1] IBM Corp, Syst & Technol Grp, Essex Jct, VT USA

来源：

IEEE INTERNATIONAL SOC CONFERENCE, PROCEEDINGS | 2004年

关键词：

autonomic computing; high performance; microarchitecture; parallel computing; SoC integration;

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

We investigate the scalability, architectural requirements, and performance characteristics of high performance systems. We use the BlueGene/L (BGAL) project as a case study for deep computing applications. This massively parallel system of 65,536 nodes with autonomic features is based on a new architecture that exploits system-on-a-chip (SoC) technology to deliver a target peak processing power of 360 teraFLOPS (trillion floating-point operations per second). BG/L is operational at a price/performance and a power consumption/performance targets unobtainable with published conventional architectures.

引用

页码：201 / 204

页数：4

共 50 条

[1] Multi-Processor Debug in SoC and Processor designs
Penner, Bill
2013 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION, AND TEST (VLSI-DAT), 2013,
[2] Unified component integration flow for multi-processor SoC design and validation
Dziri, MA
Cesário, W
Wagner, FR
Jerraya, AA
DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION, VOLS 1 AND 2, PROCEEDINGS, 2004, : 1132 - 1137
[3] A Reconfigurable Multi-Processor SoC for Media Applications
Zhu, Min
Liu, Leibo
Yin, Shouyi
Wang, Yansheng
Wang, Wenjie
Wei, Shaojun
2010 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, 2010, : 2011 - 2014
[4] Adaptive dynamic arbiter for multi-processor SoC
Xu, Yi
Li, Li
Du, Gaoming
Zhang, Yuang
Zhang, Bing
Gao, Minglun
Jisuanji Yanjiu yu Fazhan/Computer Research and Development, 2008, 45 (06): : 1085 - 1092
[5] Case study : System level design for architecture exploration of multi-processor based SoC platform
Yoon, Sung-Rok
Park, Sin-Chong
2006 8TH INTERNATIONAL CONFERENCE ON SIGNAL PROCESSING, VOLS 1-4, 2006, : 3154 - 3157
[6] Native ISS-SystemC integration for the co-simulation of multi-processor SoC
Fummi, F
Martini, S
Perbellini, G
Poncino, M
DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION, VOLS 1 AND 2, PROCEEDINGS, 2004, : 564 - 569
[7] Arbiter synthesis approach for SoC multi-processor systems
Zitouni, Abdelkrim
Tourki, Rached
COMPUTERS & ELECTRICAL ENGINEERING, 2008, 34 (01) : 63 - 77
[8] Integration of DVFS and multi CPUs Scaling in a multi-processor
Saha, Anish Kumar
Sambyo, Koj
Bhunia, C. T.
2015 INTERNATIONAL CONFERENCE ON ELECTRONIC DESIGN, COMPUTER NETWORKS & AUTOMATED VERIFICATION (EDCAV), 2015, : 78 - 81
[9] MPARM: Exploring the multi-processor SoC design space with SystemC
Benini, L
Bertozzi, D
Bogliolo, A
Menichelli, F
Olivieri, M
JOURNAL OF VLSI SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY, 2005, 41 (02): : 169 - 182
[10] Architecture for multi-processor SoC platform using dedicated channels
Lee, G
Park, SC
Fifth International Workshop on System-on-Chip for Real-Time Applications, Proceedings, 2005, : 525 - 529

← 1 2 3 4 5 →