An Energy-Efficient Dual Sampling SAR ADC with Reduced Capacitive DAC

被引：9

作者：

Kim, Binhee ^{[1
]}

Yon, Long ^{[1
]}

Yoo, Jerald ^{[1
]}

Cho, Namjun ^{[1
]}

Yoo, Hoi-Jun ^{[1
]}

机构：

[1] Korea Adv Inst Sci & Technol, Dept Elect Engn, Taejon 305701, South Korea

来源：

ISCAS: 2009 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-5 | 2009年

关键词：

D O I：

10.1109/ISCAS.2009.5117920

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper presents an energy-efficient SAR ADC which adopts reduced MSB cycling step with dual sampling of the analog signal. By sampling and holding the analog signal asymmetrically at both input sides of comparator, the MSB cycling step can be hidden by hold mode. Benefits from this technique, not only the total capacitance of DAC is reduced by half, but also the average switching energy is reduced by 68% compared with conventional SAR ADC. Moreover, switching energy distribution is more uniform over entire output code compared with previous works.

引用

页码：972 / 975

页数：4

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