An area-efficient Euclidean algorithm block for Reed-Solomon decoder

被引：0

作者：

Lee, H ^{[1
]}

机构：

[1] Univ Connecticut, Dept Elect & Comp Engn, Storrs, CT 06269 USA

来源：

ISVLSI 2003: IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI, PROCEEDINGS: NEW TRENDS AND TECHNOLOGIES FOR VLSI SYSTEMS DESIGN | 2003年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper presents a new area-efficient architrecture to implement the Euclidean algorithm, which is frequently used in Reed-Solomon decoders. The RS (255,239) decoder using the Euclidean algorithm has been implemented with 0. 13-mum CMOS technology with a supply voltage of 1.1V. We investigate hardware complexity, clock frequency and data processing rate for this Euclidean algorithm block. The results show that the total number of gates is about 44,700 and it has a data processing rate of 2.4 Gbits/s at a clock frequency of 300 MHz. As compared to the other RS decoders, it gains significant improvements in hardware complexity and latency.

引用

页码：209 / 210

页数：2