Charge Trapping Mechanism Leading to Sub-60-mV/decade-Swing FETs

被引：37

作者：

Daus, Alwin ^{[1
]}

Vogt, Christian ^{[1
]}

Munzenrieder, Niko ^{[1
,2
]}

Petti, Luisa ^{[1
]}

Knobelspies, Stefan ^{[1
]}

Cantarella, Giuseppe ^{[1
]}

Luisier, Mathieu ^{[3
]}

Salvatore, Giovanni A. ^{[1
]}

Troster, Gerhard ^{[1
]}

机构：

[1] ETH, Elect Lab, CH-8092 Zurich, Switzerland

[2] Univ Sussex, Sensor Technol Res Ctr, Dept Engn & Design, Brighton BN1 9QT, E Sussex, England

[3] ETH, Integrated Syst Lab, CH-8092 Zurich, Switzerland

来源：

IEEE TRANSACTIONS ON ELECTRON DEVICES | 2017年 / 64卷 / 07期

基金：

瑞士国家科学基金会;

关键词：

Charge trapping; FET; negative capacitance (NC); subthreshold swing (SS); thin-films; NEGATIVE CAPACITANCE; TEMPERATURE; TRANSISTORS; BEHAVIOR; DIODE;

D O I：

10.1109/TED.2017.2703914

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper, we present a novel method to reduce the subthreshold swing (SS) of FETs below 60 mV/decade. Through modeling, we directly relate trap charge movement between the gate electrode and the gate dielectric to SS reduction. We experimentally investigate the impact of charge exchange between a Cu gate electrode and a 5-nm-thick amorphous Al2O3 gate dielectric in an InGaZnO4 thin-film transistor. Positive trap charges are generated inside the gate dielectric while the semiconductor is in accumulation. During the subsequent detrapping, the SS diminishes to a minimum value of 46 mV/decade at room temperature. Furthermore, we relate the charge trapping/detrapping effects to a negative capacitance behavior of the Cu/Al2O3 metal-insulator structure.

引用

页码：2789 / 2796

页数：8

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[2]

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