Real-time unified architecture for forward/inverse discrete cosine transform in high efficiency video coding

被引：1

作者：

Abdelrasoul, Maher ^{[1
]}

Sayed, Mohammed S. ^{[1
,2
]}

Goulart, Victor ^{[1
,3
]}

机构：

[1] Egypt Japan Univ Sci & Technol, ECE Dept, Alexandria, Egypt

[2] Zagazig Univ, ECE Dept, Zagazig, Egypt

[3] Kyushu Univ, Ctr Japan Egypt Cooperat Sci & Technol, Fukuoka, Japan

来源：

IET CIRCUITS DEVICES & SYSTEMS | 2017年 / 11卷 / 04期

关键词：

video coding; codecs; discrete cosine transforms; inverse transforms; CMOS integrated circuits; inverse discrete cosine transform; real-time processing; high efficiency video coding encoder; HEVC; DCT; CMOS; video sequences; size; 65; nm; INTEGER DCT ARCHITECTURES;

D O I：

10.1049/iet-cds.2016.0423

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In High Efficiency Video Coding (HEVC) standard, higher video resolutions employ larger integer Discrete Cosine Transform (DCT)/inverse DCT (IDCT) block sizes. In this study, the authors propose two high-throughput unified DCT/IDCT architectures. The proposed architectures can process variable DCT/IDCT block sizes according to the HEVC standard. The proposed architectures were prototyped on TSMC 65nm CMOS technology. The prototyping results show that the two unified architectures have throughput of 15.24 and 16.03Gsps, respectively, and they can encode video sequences with resolutions up to 8K at 120fps and decode the same resolution at 240fps using only one circuit for both DCT and IDCT.

引用

页码：381 / 387

页数：7

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