Gross Die Per Wafer and Yield Optimization for GaAs ICs With Sub-Micron Features

被引：1

作者：

Best, Robbie M. ^{[1
]}

Tiku, Shiban K. ^{[1
]}

机构：

[1] Skyworks Solut Inc, Newbury Pk, CA 91320 USA

来源：

IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING | 2019年 / 32卷 / 04期

关键词：

Surfaces; Semiconductor device measurement; Logic gates; Pollution measurement; Integrated circuits; Resists; Lenses; Algorithms; BiHEMT; GaAs ICs; high volume manufacturing; lithography; MIM devices; reticle size; semiconductor defects; semiconductor device measurements; canon stepper; yield optimization;

D O I：

10.1109/TSM.2019.2943399

中图分类号：

T [工业技术];

学科分类号：

08 ;

摘要：

In an effort to maximize gross die per wafer (GDPW) while improving yield, various steps were taken to implement changes in the reticle layout and stepper exposure conditions across multiple designs. This allowed us to satisfy high yield goals for the BiHEMT process in a high volume manufacturing environment.

引用

页码：518 / 522

页数：5