Cache Side-Channel Attacks and Time-Predictability in High-Performance Critical Real-Time Systems

被引:21
|
作者
Trilla, David [1 ,2 ]
Hernandez, Carles [2 ]
Abella, Jaume [2 ]
Cazorla, Francisco J. [2 ,3 ]
机构
[1] Univ Politecn Cataluna, Barcelona, Spain
[2] BSC, Barcelona, Spain
[3] CSIC, IIIA, Madrid, Spain
来源
2018 55TH ACM/ESDA/IEEE DESIGN AUTOMATION CONFERENCE (DAC) | 2018年
关键词
Cache; randomization; side-channel attacks; probabilistic analysis;
D O I
10.1145/3195970.3196003
中图分类号
TP18 [人工智能理论];
学科分类号
081104 ; 0812 ; 0835 ; 1405 ;
摘要
Embedded computers control an increasing number of systems directly interacting with humans, while also manage more and more personal or sensitive information. As a result, both safety and security are becoming ubiquitous requirements in embedded computers, and automotive is not an exception to that. In this paper we analyze time-predictability (as an example of safety concern) and side-channel attacks (as an example of security issue) in cache memories. While injecting randomization in cache timing behavior addresses each of those concerns separately, we show that randomization solutions for time-predictability do not protect against side-channel attacks and vice-versa. We then propose a randomization solution to achieve both safety and security goals.
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页数:6
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