Assessment of the merits of CMOS technology scaling for analog circuit design

被引：7

作者：

Vertregt, M ^{[1
]}

Scholtens, PCS ^{[1
]}

机构：

[1] Philips Res Labs, Eindhoven, Netherlands

来源：

ESSCIRC 2004: PROCEEDINGS OF THE 30TH EUROPEAN SOLID-STATE CIRCUITS CONFERENCE | 2004年

关键词：

D O I：

10.1109/ESSCIR.2004.1356615

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Key device parameters such as drain current, transconductance, current factor, capacitance, etc. are linked to typical analog circuit level performance criteria, as a function of the CMOS technology node. Subsequently, speed and power implications for an analog-to-digital converter building block are estimated. Significant power efficiency improvements are predicted as a result of scaling to deep sub-micron technology nodes.

引用

页码：57 / 63

页数：7

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