Simulation and reliability study of Cu/Low-k devices in flip-chip packages

被引:0
作者
Zhao, JH [1 ]
Wilkerson, B [1 ]
Uehling, T [1 ]
机构
[1] Freescale Semicond Inc, Austin, TX 78735 USA
来源
STRESS-INDUCED PHENOMENA IN METALLIZATION | 2004年 / 741卷
关键词
D O I
暂无
中图分类号
TF [冶金工业];
学科分类号
0806 ;
摘要
The package impact to the mechanical integrity of the low dielectric constant (low-k) dielectrics back end of the line (BEOL) structure has been proven to be significant in recent publications. This work reports a simulation study of the package-induced delamination in low-k structures by interfacial fracture mechanics combined with multi-scale finite element method. The numerical simulation is validated by reliability test results of low-k devices in different flip-chip package configurations. The modeling result is compared to reliability test data of low-k devices in organic, ceramic flip-chip packages, and good correlation is found. Feasibility of flip-chip packaging for low-k devices is demonstrated. The risk of low-k delamination on different package configurations is rated based on both reliability data and numerical simulations.
引用
收藏
页码:52 / 61
页数:10
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