Reliability improvement of 90nm large flip chip low-k die via dicing and assembly process optimization

被引:0
|
作者
Chaware, Raghunandan [1 ]
Hoang, Lan [1 ]
机构
[1] Xillinx Inc, 2100 Logic Dr, San Jose, CA 95124 USA
来源
EPTC 2006: 8TH ELECTRONIC PACKAGING TECHNOLOGY CONFERENCE, VOLS 1 AND 2 | 2006年
关键词
D O I
暂无
中图分类号
T [工业技术];
学科分类号
08 ;
摘要
Increasing demand for higher processing speeds and enhanced electrical performance have made the use of low-k dielectric materials mandatory. For such low-k dielectric materials, enhanced dielectric properties are achieved via increased porosity of the low-k materials. These new low-k materials have different chemical, thermal, and mechanical properties than traditional dielectric materials used in older silicon technology, which in turn creates integration issues. The adhesion of the low-k layers in the silicon is also relatively weak. Due to their poor adhesion and brittle nature, low-k materials have a tendency to crack and chip during mechanical dicing with diamond blades, a widely used die singulation technique. In the case of Field Programmable Gate Array (FPGA) chips, as the demand for higher speeds and enhanced fimctionality increases, the size of the flip chip die grows accordingly to offer higher number of logic cells. Large flip chip die also requires a large package for efficient signal routing. Consequently, the stresses generated due to thermal expansion mismatch are severe, and even a small defect created on the edge of the chip during the dicing process can have a severe impact on the reliability of the flip chip device. To study the impact on flip chip reliability, two different laser dicing technologies were compared with the conventional mechanical dicing process. Other important variables tested during this study were dicing location in the saw street, lid attach dispense pattern, wafer lots, die size, and underfill. Reliability analysis indicated that for improvement of the reliability of the samples diced with mechanical dicing process, correct choice of underfill and lid attach material, optimization of the lid attach dispense pattern, and optimization of dicing location were required. In contrast, a wide reliability and process window was achieved by laser grooving process and none of the above factors tested during the study had any impact on the reliability.
引用
收藏
页码:622 / 626
页数:5
相关论文
共 50 条
  • [1] Optimization of the Thermomechanical Reliability of a 65 nm Cu/low-k Large-Die Flip Chip Package
    Ong, Jimmy M. G.
    Tay, Andrew A. O.
    Zhang, X.
    Kripesh, V.
    Lim, Y. K.
    Yeo, D.
    Chan, K. C.
    Tan, J. B.
    Hsia, L. C.
    Sohn, D. K.
    IEEE TRANSACTIONS ON COMPONENTS AND PACKAGING TECHNOLOGIES, 2009, 32 (04): : 838 - 848
  • [2] Design, assembly and reliability of large die and fine-pitch Cu/low-k flip chip package
    Ong, Yue Ying
    Ho, Soon Wee
    Vaidyanathan, Kripesh
    Sekhar, Vasarla Nagendra
    Jong, Ming Chinq
    Long, Samuel Lim Yak
    Sheng, Vincent Lee Wen
    Wai, Leong Ching
    Rao, Vempati Srinivasa
    Ong, Jimmy
    Ong, Xuefen
    Zhang, Xiaowu
    Seung, Yoon Uk
    Lau, John H.
    Lim, Yeow Kheng
    Yeo, David
    Chan, Kai Chong
    Zhang Yanfeng
    Tan, Juan Boon
    Sohn, Dong Kyun
    MICROELECTRONICS RELIABILITY, 2010, 50 (07) : 986 - 994
  • [3] Reliability of Large Die Ultra Low-k Lead-Free Flip Chip Packages
    Yip, Laurene
    2012 IEEE 62ND ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC), 2012, : 877 - 881
  • [4] Reliability of high-end flip-chip package with large 45nm ultra low-k die
    Bansal, Anurag
    Kang, Teck-Gyu
    Li, Yuan
    58TH ELECTRONIC COMPONENTS & TECHNOLOGY CONFERENCE, PROCEEDINGS, 2008, : 1357 - 1361
  • [5] A systematic approach to qualification of 90 nm Low-K flip-chip packaging
    Vissa, Uday
    Butel, Nicole
    Rowatt, James
    Thielen, Casey
    McCann, Dave
    Collins, Jeff
    56TH ELECTRONIC COMPONENTS & TECHNOLOGY CONFERENCE 2006, VOL 1 AND 2, PROCEEDINGS, 2006, : 1 - +
  • [6] Reliability evaluation of BOAC and normal pad stacked-chip packaging using 90nm low-K wafers
    Chen, K. M.
    Tang, K. H.
    Liu, J. S.
    2006 INTERNATIONAL CONFERENCE ON ELECTRONIC MATERIALS AND PACKAGING, VOLS 1-3, 2006, : 150 - +
  • [7] Overmolded flip chip packaging solution for large die FPGA with 65nm low-k dielectrics
    Yip, Laurene
    Chaware, Raghunandan
    2007 12TH INTERNATIONAL SYMPOSIUM ON ADVANCED PACKAGING MATERIALS: PROCESSES, PROPERTIES, AND INTERFACES, 2007, : 1 - 4
  • [8] Low-K Flip Chip Board Level Reliability on 65nm Technology
    Tsao, Pei-Haw
    Kiang, Bill
    Wu, Kenneth
    Chang, Abel
    Yuan, Tsorng-Dih
    57TH ELECTRONIC COMPONENTS & TECHNOLOGY CONFERENCE, 2007 PROCEEDINGS, 2007, : 110 - +
  • [9] Advanced HiCTE ceramic flip-chipping of 90nm Cu/Low-K device: A novel material, package structure, and process optimization study
    Chungpaiboonpatana, S
    Shi, FG
    55th Electronic Components & Technology Conference, Vols 1 and 2, 2005 Proceedings, 2005, : 1491 - 1496
  • [10] Reliability improvement of 90nm-node Cu/Low-k interconnects
    Matsumoto, S
    Ishii, A
    Tomito, K
    Hashimoto, K
    Nishioka, Y
    Sekiguchi, M
    Iwasaki, A
    Sono, S
    Satake, T
    Okazaki, G
    Fujisawa, M
    Matsumoto, M
    Yamamoto, S
    Matsuura, M
    PROCEEDINGS OF THE IEEE 2003 INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE, 2003, : 262 - 264