共 50 条
- [1] Optimization of the Thermomechanical Reliability of a 65 nm Cu/low-k Large-Die Flip Chip Package IEEE TRANSACTIONS ON COMPONENTS AND PACKAGING TECHNOLOGIES, 2009, 32 (04): : 838 - 848
- [3] Reliability of Large Die Ultra Low-k Lead-Free Flip Chip Packages 2012 IEEE 62ND ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC), 2012, : 877 - 881
- [4] Reliability of high-end flip-chip package with large 45nm ultra low-k die 58TH ELECTRONIC COMPONENTS & TECHNOLOGY CONFERENCE, PROCEEDINGS, 2008, : 1357 - 1361
- [5] A systematic approach to qualification of 90 nm Low-K flip-chip packaging 56TH ELECTRONIC COMPONENTS & TECHNOLOGY CONFERENCE 2006, VOL 1 AND 2, PROCEEDINGS, 2006, : 1 - +
- [6] Reliability evaluation of BOAC and normal pad stacked-chip packaging using 90nm low-K wafers 2006 INTERNATIONAL CONFERENCE ON ELECTRONIC MATERIALS AND PACKAGING, VOLS 1-3, 2006, : 150 - +
- [7] Overmolded flip chip packaging solution for large die FPGA with 65nm low-k dielectrics 2007 12TH INTERNATIONAL SYMPOSIUM ON ADVANCED PACKAGING MATERIALS: PROCESSES, PROPERTIES, AND INTERFACES, 2007, : 1 - 4
- [8] Low-K Flip Chip Board Level Reliability on 65nm Technology 57TH ELECTRONIC COMPONENTS & TECHNOLOGY CONFERENCE, 2007 PROCEEDINGS, 2007, : 110 - +
- [9] Advanced HiCTE ceramic flip-chipping of 90nm Cu/Low-K device: A novel material, package structure, and process optimization study 55th Electronic Components & Technology Conference, Vols 1 and 2, 2005 Proceedings, 2005, : 1491 - 1496
- [10] Reliability improvement of 90nm-node Cu/Low-k interconnects PROCEEDINGS OF THE IEEE 2003 INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE, 2003, : 262 - 264