Closed-Loop Nonlinear Modeling of ΣΔ Fractional-N Frequency Synthesizers

Nonlinear, time-varying nature of synthesizer building blocks such as phase frequency detectors (PFD), charge pump and frequency dividers can increase close-in phase noise and enhance spurious tones due to intermodulation of high frequency quantization noise and tonal content; therefore, an accurate simulation model is critical for successful implementation of loop parameters and bandwidth widening techniques. In this paper inherent non-uniform sampling of the PFD is modeled through an event-driven dual-iteration based technique. The proposed technique generates a vector of piece-wise linear time-voltage pairs, defining the VCO control voltage. A flexible third-order Sigma Delta modulated RF synthesizer core with integrated loop filter and LC-tank VCO is designed and fabricated in 0.13-mu m CMOS process in order to validate the technique experimentally. The proposed modeling technique was able to predict in-band spur power levels with 1.8 dB accuracy, and spur frequency offsets with lower than 400Hz accuracy with several programmable non-idealities enabled.