Multichannel sequential pulse accumulator with a two-group memory addressing

被引:0
作者
Sinyavskii, VI
Manapov, RA
机构
[1] Kazan State Univ, Kazan 420008, Tatarstan, Russia
[2] Russian Acad Sci, Kazan Res Ctr, Kazan Engn Phys Inst, Kazan 420029, Tatarstan, Russia
关键词
D O I
暂无
中图分类号
T [工业技术];
学科分类号
08 ;
摘要
Based on the two-group RAM IC addressing principle, a multichannel (256 channels) sequential data accumulator applying KP537PY14A RAM IC with one-bit memory (4K x 1) is proposed. The channel capacity is 2(16)-1, and the input pulse repetition frequency is up to 62 kHz.
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页码:192 / 196
页数:5
相关论文
共 3 条
  • [1] GORN LS, 1987, PROGRAMMNO UPRAVLYAE, P256
  • [2] SINYAVSKII VI, 1991, PRIB TEKH EKSP, P55
  • [3] SINYAVSKII VI, 1996, PRIB TEKH EKSP, P77