A High Speed Subthreshold SRAM Cell Design

被引：5

作者：

Ahmadimehr, Amir-Reza ^{[1
]}

Ebrahimi, Behzad ^{[1
]}

Afzali-Kusha, Ali ^{[1
]}

机构：

[1] Univ Tehran, Sch Elect & Comp Engn, Nanoelect Ctr Excellence, Tehran 14174, Iran

来源：

2009 1ST ASIA SYMPOSIUM ON QUALITY ELECTRONIC DESIGN | 2009年

关键词：

D O I：

10.1109/ASQED.2009.5206306

中图分类号：

TP301 [理论、方法];

学科分类号：

081202 ;

摘要：

In this paper, we propose a subthreshold SRAM cell structure which can be read differentially. The main advantage of the cell is its high read current while the static noise margin and power consumption are reasonable. The cell is suitable for high performance applications where the speed is of prime concern. To assess the efficiency of the proposed cell, we compare its characteristics to three subthreshold SRAM cell structures recently introduced in the literature. The cells are implemented in both the bulk and SOI-FinFET technologies at the node of 32nm.

引用

页码：9 / 13

页数：5

共 8 条

[1]

[Anonymous], BERKELEY PREDICTIVE

[2]

[Anonymous], ISSCC

[3] A 256-kb 65-nm sub-threshold SRAM design for ultra-low-voltage operation [J].

Calhoun, Benton Highsmith ;

Chandrakasan, Anantha P. .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2007, 42 (03) :680-688

[4]

GUO Z, 2005, FINFET BASED SRAM DE, P8

[5]

Ik Joon Chang, 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, P388

[6] Double gate-MOSFET subthreshold circuit for ultralow power applications [J].

Kim, JJ ;

Roy, K .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 2004, 51 (09) :1468-1474

[7] STATIC-NOISE MARGIN ANALYSIS OF MOS SRAM CELLS [J].

SEEVINCK, E ;

LIST, FJ ;

LOHSTROH, J .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1987, 22 (05) :748-754

[8]

Tang S. H., 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177), P118, DOI 10.1109/ISSCC.2001.912568

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