A Threshold Voltage Model of Tri-Gate Junctionless Field-Effect Transistors Including Substrate Bias Effects

被引：23
|
作者：
Gola, Deepti [1 ]
Singh, Balraj [2 ]
Tiwari, Pramod Kumar [1 ]
机构：
[1] IIT Patna, Dept Elect Engn, Patna 801103, Bihar, India
[2] GB Pant Engn Coll, Dept Elect & Commun Engn, Pauri Garhwal 246194, India
来源：
IEEE TRANSACTIONS ON ELECTRON DEVICES | 2017年 / 64卷 / 09期
关键词：
Drain-induced barrier lowering (DIBL); junctionless field-effect transistor (JLFET); substrate bias; threshold voltage; tri-gate (TG); SOI MOSFETS;
D O I：
10.1109/TED.2017.2722044
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
In this paper, the influence of substrate bias voltage and substrate-induced surface potential (SISP) on threshold voltage of tri-gate junctionless field-effect transistors (TG-JLFETs) has been investigated. For this purpose, a quasi-3-D threshold voltage model of TG-JLFETs is presented considering the effects of both back-bias voltage and a lightly doped substrate. To incorporate the effect of SISP on the threshold voltage, the boundary conditions at the silicon-buried oxide interface have been modified accounting for the potential difference between substrate surface and substrate bulk. Model results are compared with the simulation results obtained using 3-D visual TCAD device simulator from Cogenda.
引用
收藏
页码：3632 / 3638
页数：7
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