On effective criterion of path selection for delay testing

被引:0
|
作者
Fukunaga, M [1 ]
Kajihara, S [1 ]
Takeoka, S [1 ]
Yosimura, S [1 ]
机构
[1] Kyushu Inst Technol, Dept Comp Sci & Elect, Kitakyushu, Fukuoka, Japan
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中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
Since a logic circuit often has too many paths to test delay of all paths in the circuit, it is necessary for path delay testing to limit the number of paths to be tested. Paths to be tested should be ones with large delay that more likely cause a fault. In addition, a test set for the paths are required to detect other models of faults as many as possible. In this paper, we investigate criteria or path selection for path delay testing. We first define typical two criteria to be investigated here, and then experimentally show the feature of paths selected with each criterion, with respect to fault coverage of other delay fault models. From our experiments, we observe that test patterns for the longest paths cannot cover many other faults such as gate delay faults or segment delay faults.
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收藏
页码:757 / 762
页数:6
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