A data-interlacing architecture with two-dimensional data-reuse for full-search block-matching algorithm

被引：57
|
作者：
Lai, YK [1 ]
Chen, LG
机构：
[1] Chang Gung Univ, Dept Elect Engn, Taipei, Taiwan
[2] Natl Taiwan Univ, Dept Elect Engn, Taipei 10764, Taiwan
来源：
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY | 1998年 / 8卷 / 02期
关键词：
architecture; blocking matching algorithm; motion estimation; video coding; VLSI;
D O I：
10.1109/76.664095
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
This paper describes a data-interlacing architecture with two-dimensional (2-D) data-reuse fur fun-search block-matching algorithm, Based on a one-dimensional processing element (PE) array and two data-interlacing shift-register arrays, the proposed architecture can efficiently reuse data to decrease external memory accesses and save the pin counts, It also achieves 100% hardware utilization and a high throughput rate, In addition, the same chips can Pre cascaded for different block sizes, search ranges, and pixel rates.
引用
收藏
页码：124 / 127
页数：4
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