A VLSI architecture of spatial combinative lifting algorithm based 2-D DWT/IDWT

被引：0
|
作者：
Liu, LB [1 ]
Wang, XJ [1 ]
Meng, HY [1 ]
Zhang, L [1 ]
Wang, ZH [1 ]
Chen, HY [1 ]
机构：
[1] Tsing Hua Univ, Inst Microelect, Beijing 100084, Peoples R China
来源：
APCCAS 2002: ASIA-PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS, VOL 2, PROCEEDINGS | 2002年
关键词：
D O I：
暂无
中图分类号：
TP [自动化技术、计算机技术];
学科分类号：
0812 ;
摘要：
The Discrete Wavelet Transform (DWT) is the basis for many image compression techniques, such as JPEG2000, MPEG-4, etc. Spatial Combinative Lifting Algorithm (SCLA) based 2-D DWT/IDWT requires fewer computations than the conventional Lifting Based Implementation (LBI). In comparison with the LBI, SCLA with the 9/7 filter has 7/12 the number of multiplications. This paper proposes a novel VLSI architecture to compute multilevel SCLA based 2-D DWT/IDWT with the 9/7 filter. The line based transform is integrated with the SCLA scheme to reduce the hardware cost and achieve higher hardware utilization. Efficient organization of six line-buffer memories is used to address the high memory bandwidth requirements. This architecture can be used as a compact and efficient core for JPEG2000 VLSI implementation and various real-time image/video applications.
引用
收藏
页码：299 / 304
页数：6
相关论文
共 50 条
  • [1] A VLSI chip of SCLA based 2-d DWT/IDWT
    Liu, LB
    Chen, N
    Meng, HY
    Zhang, L
    Wang, ZH
    Chen, HY
    2003 5TH INTERNATIONAL CONFERENCE ON ASIC, VOLS 1 AND 2, PROCEEDINGS, 2003, : 898 - 901
  • [2] An efficient line based VLSI architecture for 2-D lifting DWT
    Jung, GC
    Jin, DY
    Park, SM
    2004 47TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL II, CONFERENCE PROCEEDINGS, 2004, : 249 - 252
  • [3] Efficient line-based vlsi architecture for 2-d lifting dwt
    Wang, Keyan
    Wu, Chengke
    Liu, Kai
    Li, Yunsong
    Jeong, Jechang
    2006 IEEE INTERNATIONAL CONFERENCE ON IMAGE PROCESSING, ICIP 2006, PROCEEDINGS, 2006, : 2129 - +
  • [4] Novel VLSI architecture of 2-D DWT/IDWT for JPEG2000 based on diagonal storage
    Qin, X
    Yan, XL
    Yang, CP
    Zhao, X
    2004: 7TH INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUITS TECHNOLOGY, VOLS 1- 3, PROCEEDINGS, 2004, : 1657 - 1660
  • [5] Design of highly efficient VLSI architectures for 2-D DWT and 2-D IDWT
    Chang, YN
    Li, YS
    SIPS 2001: IEEE WORKSHOP ON SIGNAL PROCESSING SYSTEMS: DESIGN AND IMPLEMENTATION, 2001, : 133 - 140
  • [6] Flipping-based High Speed VLSI Architecture for 2-D Lifting DWT
    Darji, A. D.
    Shashikanth, Konale
    Limaye, Ankur
    Merchant, S. N.
    Chandorkar, A. N.
    2014 IEEE 57TH INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS (MWSCAS), 2014, : 193 - 196
  • [7] Hardware Efficient Recursive VLSI Architecture for Multilevel Lifting 2-D DWT
    Darji, A. D.
    Trivedi, Nisarg
    Merchant, S. N.
    Chandorkar, A. N.
    2012 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS 2012), 2012, : 1014 - 1017
  • [8] High Performance VLSI Architecture for 2-D DWT Using Lifting Scheme
    Mithun, R.
    Hegde, Ganapathi
    2015 INTERNATIONAL CONFERENCE ON VLSI SYSTEMS, ARCHITECTURE, TECHNOLOGY AND APPLICATIONS (VLSI-SATA), 2015,
  • [9] A Parallel-based Lifting Algorithm and VLSI Architecture for DWT
    Xiong Chengyi Tian Jinwen Liu Jian Gao Zhirong (The State Key Lab of Education Commission for Image Processing and Intelligent Control
    Journal of Electronics(China), 2006, (02) : 244 - 248
  • [10] A Parallel-based Lifting Algorithm and VLSI Architecture for DWT
    Xiong Chengyi Tian Jinwen Liu Jian Gao Zhirong The State Key Lab of Education Commission for Image Processing and Intelligent Control Institute of Pattern Recognition Artificial Intelligence Huazhong Univ of Science Tech Wuhan China College of Electronic Info Eng SouthCenter Univ for Nationalities Wuhan China Dept of Computer Science Wuhan Univ of Science Eng Wuhan China
    JournalofElectronics, 2006, (02) : 244 - 248
12345