SAMPA Chip: the New 32 Channels ASIC for the ALICE TPC and MCH Upgrades

被引:28
|
作者
Adolfsson, J. [1 ]
Ayala Pabon, A. [2 ]
Bregant, M. [3 ]
Britton, C. [4 ]
Brulin, G. [5 ]
Carvalho, D. [2 ]
Chambert, V. [5 ]
Chinellato, D. [6 ]
Espagnon, B. [5 ]
Hernandez Herrera, H. D. [2 ]
Ljubicic, T. [7 ]
Mahmood, S. M. [8 ]
Mjornmark, U. [1 ]
Moraes, D. [9 ]
Munhoz, M. G. [3 ]
Noel, G. [5 ]
Oskarsson, A. [1 ]
Osterman, L. [1 ]
Pilyar, A. [10 ]
Read, K. [4 ]
Ruette, A. [6 ]
Russo, P. [5 ]
Sanches, B. C. S. [2 ]
Severo, L. [2 ]
Silvermyr, D. [1 ]
Suire, C. [5 ]
Tambave, G. J. [11 ]
Tun-Lanoe, K. M. M. [5 ]
van Noije, W. [2 ]
Velure, A. [11 ]
Vereschagin, S. [10 ]
Wanlin, E. [5 ]
Weber, T. O. [12 ]
Zaporozhets, S. [10 ]
机构
[1] Lund Univ, Dept Phys, Div Particle Phys, Box118, SE-22100 Lund, Sweden
[2] Univ Sao Paulo, Escola Politecn, Sao Paulo, Brazil
[3] Univ Sao Paulo, Inst Fis, Rua Matao 1371, Sao Paulo, Brazil
[4] Oak Ridge Natl Lab, Oak Ridge, TN 37831 USA
[5] Univ Paris 11, IPNO, CNRS IN2P3, 15 Rue Georges Clemenceau, F-91406 Orsay, France
[6] Univ Estadual Campinas, Inst Fis Gleb Wataghin, R Sergio Buarque Holanda,777, Campinas, Brazil
[7] Brookhaven Natl Lab, Upton, NY 11973 USA
[8] Univ Oslo, POB 1048, NO-0316 Oslo, Norway
[9] ITA0, Sao Jose Dos Campos, Brazil
[10] Joint Inst Nucl Res, Joliot Curie 6, Dubna, Moscow Region, Russia
[11] Univ Bergen, POB 7800, NO-5020 Bergen, Norway
[12] UFSC Campus Ararangua, Dept Comp, Rua Pedro Joao Pereira,150, Ararangua, SC, Brazil
来源
JOURNAL OF INSTRUMENTATION | 2017年 / 12卷
关键词
CMOS readout of gaseous detectors; Front-end electronics for detector readout; Analogue electronic circuits;
D O I
10.1088/1748-0221/12/04/C04008
中图分类号
TH7 [仪器、仪表];
学科分类号
0804 ; 080401 ; 081102 ;
摘要
This paper presents the test results of the second prototype of SAMPA, the ASIC designed for the upgrade of read-out front end electronics of the ALICE Time Projection Chamber (TPC) and Muon Chamber (MCH). SAMPA is made in a 130 nm CMOS technology with 1.25V nominal voltage supply and provides 32 channels, with selectable input polarity, and three possible combinations of shaping time and sensitivity. Each channel consists of a Charge Sensitive Amplifier, a semi-Gaussian shaper and a 10-bit ADC; a Digital Signal Processor provides digital filtering and compression capability. In the second prototype run both full chip and single test blocks were fabricated, allowing block characterization and full system behaviour studies. Experimental results are here presented showing agreement with requirements for both the blocks and the full chip.
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页数:10
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