A Novel Ultra High Speed and Configurable Discrete Wavelet Packet Transform Architecture

This work is dedicated to present a new architecture of Discrete Wavelet Packet Transform (DWPT) implemented in FPGA using a parallel direct FIR () filter. The main target of our architecture is to provide an effective performance trade-off, where it significantly increases the throughput with a restricted amount of hardware. It is smartly connect based on low-pass and high-pass filters in the Mallat-tree algorithm by a clever sharing of the hardware resources. This architecture is fully configurable in synthesis according to parallel degree, the tree depth (number of tree levels), the order of the filters and the filter quantization coefficient. Consequently, the simulation results accelerated to an approximate value of P*(Frequency). Furthermore, the tree depth and filters order has little impact (only due to place and route variations) on throughput. This architecture was synthesized using Altera Quartus prime lite edition targeting an Altera Cyclone IV - (FPGA) and it was developed in VHDL at RTL level modeling.