Embedded Multidie Interconnect Bridge-A Localized, High-Density Multichip Packaging Interconnect

被引：55

作者：

Mahajan, Ravi ^{[1
]}

Qian, Zhiguo ^{[1
]}

Viswanath, Ram S. ^{[1
]}

Srinivasan, Sriram ^{[1
]}

Aygun, Kemal ^{[1
]}

Jen, Wei-Lun ^{[1
]}

Sharan, Sujit ^{[1
]}

Dhall, Ashish ^{[1
]}

机构：

[1] Intel Corp, Dept Assembly & Test Technol Dev, Chandler, AZ 85226 USA

来源：

IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY | 2019年 / 9卷 / 10期

关键词：

Back end of line (BEOL); CPU; dense multichip packaging (MCP); DRAM; embedded multidie interconnect bridge (EMIB); high bandwidth memory generation 2 (HBM2); MCP; through-silicon via (TSV);

D O I：

10.1109/TCPMT.2019.2942708

中图分类号：

T [工业技术];

学科分类号：

08 ;

摘要：

This article provides an overview of the embedded multidie interconnect bridge (EMIB) multichip packaging (MCP) technology. EMIB is a unique packaging paradigm that provides very high-density interconnects (currently in the range of 500-1000 I/O/mm) localized in between two devices, thus enabling high-bandwidth (BW) on-package links while leaving the rest of the package structures and designs unaffected. The construction of the silicon bridge and the package to allow high BW electrical signaling between two dies is discussed in detail. Examples of the EMIB implementations for the links between the field-programmable gate array (FPGA) logic and high bandwidth memory generation 2 (HBM2) memory stacks, graphics die and HBM2 memory stacks, FPGA logic die, and high-performance transceiver die are described. EMIB packaging is compared with similar high-density interconnect technologies such as silicon interposer with through-silicon vias (TSVs) and other fan-out-based package technologies. Design optimization strategies for power delivery and I/O routing in the presence of an embedded bridge are highlighted.

引用

页码：1952 / 1962

页数：11

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