SAT-Based ATPG Testing of Inter- and Intra-Gate Bridging Faults

被引：3

作者：

Nakura, Toru ^{[1
]}

Tatemura, Yutaro

Fey, Goerschwin ^{[2
,3
]}

Ikeda, Makoto ^{[1
]}

Komatsu, Satoshi ^{[3
]}

Asada, Kunihiro ^{[1
]}

机构：

[1] Univ Tokyo, VDEC, Tokyo 1138654, Japan

[2] Univ Bremen, Inst Comp Sci, D-28359 Bremen, Germany

[3] Univ Tokyo, D2T VDEC, Tokyo, Japan

来源：

2009 EUROPEAN CONFERENCE ON CIRCUIT THEORY AND DESIGN, VOLS 1 AND 2 | 2009年

关键词：

IDDQ; ATPG; SAT; bridging fault; intra-/inter-gate; GENERATION;

D O I：

10.1109/ECCTD.2009.5275065

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents an ATPG framework for IDDQ testing of both intra- and inter-gate bridging faults. The framework integrates random simulation and a deterministic stage using Boolean SATisfiability (SAT) as the underlying engine. This decides whether a fault is testable or untestable. In this way, we conduct an exact search for test patterns for IDDQ testing of both intra- and inter-gate bridging fault detection.

引用

页码：643 / +

页数：2

共 23 条

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