Re-synthesis approach to Engineering Change Orders (ECOs)

被引:0
作者
Vaidyanathan, Athmanathan [1 ]
Varde, Amit [1 ]
Iyengar, Sudarshan [1 ]
Settikeri, Srikanth [1 ]
Subramaniam, Swetha [1 ]
机构
[1] Microchip Technol Inc, 2355 W Chandler Blvd, Chandler, AZ 85224 USA
来源
PROCEEDINGS OF THE FOURTH IASTED INTERNATIONAL CONFERENCE ON CIRCUITS, SIGNALS, AND SYSTEMS | 2006年
关键词
Engineering Change Order; design synthesis tool; Automatic Placement and Routing; clock tree synthesis;
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Implementing Engineering Change Orders (ECOs) using only spare gates and metal masks is part of every designer's job. With a Register Transfer Logic (RTL) design methodology, if RTL synthesis tools were used for development of the original design, it becomes very cumbersome to track the RTL changes to the gate-level netlist. This paper will discuss a new approach for developing tools to implement complex ECOs with minimal designer interference. A semi-automated technique to implement an ECO through automatic iterative constraining of RTL synthesis and Automatic Placement and Routing (APR) tools will be presented. The paper will show how, while designer intervention may not be reduced to zero, it is significantly less when compared to all-manual methods.
引用
收藏
页码:120 / +
页数:2
相关论文
共 8 条
[1]  
Brayton R. K., 1987, Design Systems for VLSI Circuits. Logic Synthesis and Silicon Compilation. Proceedings of the NATO Advanced Study Institute, P197
[2]  
Cormen T. H., 1990, INTRO ALGORITHMS
[3]   OPTIMUM BUFFER CIRCUITS FOR DRIVING LONG UNIFORM LINES [J].
DHAR, S ;
FRANKLIN, MA .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1991, 26 (01) :32-40
[4]   RECENT ADVANCES IN VLSI LAYOUT [J].
KUH, ES ;
OHTSUKI, T .
PROCEEDINGS OF THE IEEE, 1990, 78 (02) :237-263
[5]  
Neil H. E. W., 1985, PRINCIPLES CMOS VLSI
[6]  
PULLELA S, 1993, P IEEE INT C COMP AI, P556
[7]  
[No title captured]
[8]  
[No title captured]