CFET Standard-cell design down to 3Track height for node 3nm and below

被引：12

作者：

Sherazi, S. M. Y. ^{[1
]}

Kyu, J. ^{[1
]}

Debacker, P. ^{[1
]}

Matti, L. ^{[1
]}

Verkest, D. ^{[1
]}

Mocuta, A. ^{[1
]}

Kim, R. H. ^{[1
]}

Spessot, A. ^{[1
]}

Dounde, A. ^{[1
]}

Ryckaert, J. ^{[1
]}

机构：

[1] IMEC, Dept Log Technol, Kapeldreef 75, B-3001 Heverlee, Belgium

来源：

DESIGN-PROCESS-TECHNOLOGY CO-OPTIMIZATION FOR MANUFACTURABILITY XIII | 2019年 / 10962卷

关键词：

Standard Cell Design; Track height reduction; Scaling using DTCO; Advance technology node; Tight metal pitch; Multi-level middle of line; Scaling boosters; Complementary FET (CFET);

D O I：

10.1117/12.2514571

中图分类号：

TP39 [计算机的应用];

学科分类号：

081203 ; 0835 ;

摘要：

Advanced technology nodes are based on nFET and pFET fins, which are fabricated on the same Silicon level of the wafer. However, in a complimentary FET (CFET) technology the nFET and pFET devices are stacked on top of each other [1]. This provides a significant area reduction mainly driven by a simplified transistor terminal access and the removal of the lateral physical separation between the two transistors. The combination of the CFET with buried power rails can reduce the track height of the cells and the elusive 3 Track standard cell is seen to be a possibility.

引用

页数：12