Efficient Reverse Converter Designs for the New 4-Moduli Sets {2n-1, 2n, 2n+1, 22n+1-1} and {2n-1, 2n+1, 22n, 22n+1} Based on New CRTs

被引:86
|
作者
Molahosseini, Amir Sabbagh [1 ]
Navi, Keivan [2 ]
Dadkhah, Chitra [3 ]
Kavehei, Omid [4 ]
Timarchi, Somayeh [2 ]
机构
[1] Islamic Azad Univ, Dept Comp Engn, Sci & Res Branch, Tehran 1477893855, Iran
[2] Shahid Beheshti Univ, Dept Elect & Comp Engn, GC, Tehran 1983963113, Iran
[3] KN Toosi Univ Technol, Dept Elect Engn, Tehran 1969764499, Iran
[4] Univ Adelaide, Sch Elect & Elect Engn, Ctr High Performance Integrated Technol & Syst, Adelaide, SA 5005, Australia
关键词
Computer arithmetic; new Chinese remainder theorems (New CRTs); residue arithmetic; reverse converter; residue number system (RNS); TO-BINARY CONVERTER; HIGH-SPEED; NUMBER SYSTEM; RESIDUE; RNS; 2(N+1)-1;
D O I
10.1109/TCSI.2009.2026681
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
In this paper, we introduce two new 4-moduli sets {2(n)-1, 2(n), 2(n)+1, 2(2n+1)-1} and {2(n)-1, 2(n)+1, 2(2n), 2(2n)+1} for developing efficient large dynamic range (DR) residue number systems (RNS). These moduli sets consist of simple and well-formed moduli which can result in efficient implementation of the reverse converter as well as internal RNS arithmetic circuits. The moduli set {2(n) - 1, 2(n), 2(n) + 1, 2(2n+1) - 1} has 5n-bit DR and it can result in a fast RNS arithmetic unit, while the 6n-bit DR moduli set {2(n) - 1, 2(n) + 1, 2(2n), 2(2n) + 1} is a conversion friendly moduli set which can lead to a high-speed and low-cost reverse converter design. Next, efficient reverse converters for the proposed moduli sets based on new Chinese remainder theorems (New CRTs) are presented. The converter for the moduli set {2(n) - 1,2(n), 2(n) + 1, 2(2n+1) - 1} is derived by New CRT-II with better performance compared to the reverse converter for the latest introduced 5n-bit DR moduli set {2(n) - 1, 2(n), 2(n) + 1, 2(2n-1) - 1}. Also, New CRT-I is used to achieve a high-performance reverse converter for the moduli set {2(n) - 1, 2(n) + 1, 2(2n), 2(2n) + 1}. This converter has less conversion delay and lower hardware requirements than the reverse converter for a recently suggested 6n-bit DR moduli set {2(n) - 1, 2(n) + 1, 2(2n) - 2, 2(2n+1) - 3}
引用
收藏
页码:823 / 835
页数:13
相关论文
共 50 条
  • [31] Efficient methods in converting to modulo 2n+1 and 2n-1
    Manochehri, Kooroush
    Pourmozafari, Saadat
    Sadeghian, Babak
    THIRD INTERNATIONAL CONFERENCE ON INFORMATION TECHNOLOGY: NEW GENERATIONS, PROCEEDINGS, 2006, : 178 - +
  • [32] Efficient Reverse Converter Design for New Adaptable Four-Moduli Set {2n+k, 2n+1,2n-1,22n+1}
    Sheu, Ming-Hwa
    Kuo, Yuan-Ching
    Lin, Su-Hon
    Siao, Siang-Min
    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, 2013, E96A (07) : 1571 - 1578
  • [33] A Reverse Converter for Three-Moduli Set (2k, 2n-1, 2n+1), k < n
    Hiasat, Ahmad
    2019 IEEE JORDAN INTERNATIONAL JOINT CONFERENCE ON ELECTRICAL ENGINEERING AND INFORMATION TECHNOLOGY (JEEIT), 2019, : 548 - 553
  • [34] A New High-Speed, Low-Area Residue-to-Binary Converter For the Moduli Set {24n, 22n+1, 2n+1, 2n-1} Based on CRT-1
    Akbari, Ali
    Hosseinzadeh, Mehdi
    TaghipourEivazi, Shiva
    Jassbi, Somayyeh Jafarali
    CIRCUITS SYSTEMS AND SIGNAL PROCESSING, 2021, 40 (11) : 5773 - 5786
  • [35] Efficient two-level reverse converters for the four-moduli set {2n-1, 2n-1, 2n-1-1, 2n+1-1}
    Obeidi Daghlavi, Mohammad
    Noorimehr, Mohammad Reza
    Esmaeildoust, Mohammad
    ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, 2021, 108 (01) : 75 - 87
  • [36] A VLSI Efficient Programmable Power-of-Two Scaler for {2n-1, 2n, 2n+1} RNS
    Low, Jeremy Yung Shern
    Chang, Chip-Hong
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2012, 59 (12) : 2911 - 2919
  • [37] High Speed Residue to Binary Converter for the New Four-Moduli Set {22n, 2n + 1, 2n/2 + 1, 2n/2−1}
    M. R. Noorimehr
    M. Hosseinzadeh
    R. Farshidi
    Arabian Journal for Science and Engineering, 2014, 39 : 2887 - 2893
  • [38] An Efficient FPGA Design of Residue-to-Binary Converter for the Moduli Set {2n+1, 2n-1}
    Gbolagade, Kazeem Alagbe
    Voicu, George Razvan
    Cotofana, Sorin Dan
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2011, 19 (08) : 1500 - 1503
  • [39] Design of Reverse Converters for a New Flexible RNS Five-Moduli Set {2k, 2n-1, 2n+1, 2n+1-1, 2n-1-1} (n Even)
    Patronik, Piotr
    Piestrak, Stanisaw J.
    CIRCUITS SYSTEMS AND SIGNAL PROCESSING, 2017, 36 (11) : 4593 - 4614
  • [40] Simple, Fast, and Exact RNS Scaler for the Three-Moduli Set {2n-1, 2n, 2n+1}
    Chang, Chip-Hong
    Low, Jeremy Yung Shern
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2011, 58 (11) : 2686 - 2697