Molybdenum gate technology for ultrathin-body MOSFETs and FinFETs

被引:41
作者
Ha, D [1 ]
Takeuchi, H
Choi, YK
King, TJ
机构
[1] Univ Calif Berkeley, Dept Elect Engn & Comp Sci, Berkeley, CA 94720 USA
[2] Korea Adv Inst Sci & Technol, Dept Elect Engn & Comp Sci, Taejon 305701, South Korea
关键词
complementary metal-oxide-semiconductor; (CMOS); dry etching; FinFET; fully depleted silicon-on-insulator (FD SOI); molybdenum metal gate; sputter; ultrathin body;
D O I
10.1109/TED.2004.839752
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Damage-free sputter deposition and highly selective dry-etch processes have been developed for molybdenum (Mo) metal gate technology, for application to fully depleted silicon-on-insulator ( devices such as the ultrathin body (UTB) MOSFET and double-gate FinFET. A plasma charge trap effectively eliminates high-energy particle bombardment during Mo sputtering; hence the gate-dielectric integrity (TDDB, Q(BD)) is significantly improved and the field-effect mobility in Mo-gated MOSFETs follows the universal mobility curve. The effects of etch process parameters such as chlorine (Cl-2) and oxygen (O-2) gas flow rate, and source and bias radio frequence powers, were investigated in order to optimize the Mo etch rate and selectivity to SiO2. A highly selective etch process was successfully applied to pattern Mo gate electrodes for UTB MOSFETs and FinFETs without leaving any residue or stringers. Measured electrical characteristics and physical analysis results are discussed.
引用
收藏
页码:1989 / 1996
页数:8
相关论文
共 29 条
  • [1] [Anonymous], P ESSDERC
  • [2] MOSFET scalability limits and "new frontier" devices
    Antoniadis, DA
    [J]. 2002 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS, 2002, : 2 - 5
  • [3] Gate length scaling and threshold voltage control of double-gate MOSFETs.
    Chang, L
    Tang, S
    King, TJ
    Bokor, J
    Hu, C
    [J]. INTERNATIONAL ELECTRON DEVICES MEETING 2000, TECHNICAL DIGEST, 2000, : 719 - 722
  • [4] Choi YK, 2002, INTERNATIONAL ELECTRON DEVICES 2002 MEETING, TECHNICAL DIGEST, P259, DOI 10.1109/IEDM.2002.1175827
  • [5] Nanoscale ultrathin body PMOSFETs with raised selective germanium source/drain
    Choi, YK
    Ha, DW
    King, TJ
    Hu, CM
    [J]. IEEE ELECTRON DEVICE LETTERS, 2001, 22 (09) : 447 - 448
  • [6] CULLITY NJB, 2001, ELEMENTS XRAY DIFFRA
  • [7] Device scaling limits of Si MOSFETs and their application dependencies
    Frank, DJ
    Dennard, RH
    Nowak, E
    Solomon, PM
    Taur, Y
    Wong, HSP
    [J]. PROCEEDINGS OF THE IEEE, 2001, 89 (03) : 259 - 288
  • [8] FUYUKI T, 1992, IEICE T ELECTRON, VE75C, P1013
  • [9] Scaling challenges and device design requirements for high performance sub-50 nm gate length planar CMOS transistors
    Ghani, T
    Mistry, K
    Packan, P
    Thompson, S
    Stettler, M
    Tyagi, S
    Bohr, M
    [J]. 2000 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS, 2000, : 174 - 175
  • [10] HA D, 2003, P INT C SOL STAT DEV, P782