Perspective of FinFETs for analog applications

被引:39
作者
Kilchytska, V [1 ]
Collaert, N [1 ]
Rooyackers, R [1 ]
Lederer, D [1 ]
Raskin, JP [1 ]
Flandre, D [1 ]
机构
[1] Catholic Univ Louvain, Microelect Lab, B-1348 Louvain, Belgium
来源
ESSDERC 2004: PROCEEDINGS OF THE 34TH EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE | 2004年
关键词
D O I
10.1109/ESSDER.2004.1356489
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
FinFETs are known to be one of the most promising technological solutions to create high-performance ultra-scaled Si MOSFETs. In this paper we present the first detailed experimental investigation of the analog performance of FinFETs with channel lengths down to 50nm. We demonstrate that such devices have very strong potential for analog applications, mainly thanks to a super-high value of the Early Voltage and hence intrinsic gain, which they can provide. The impact of Fin width on device characteristics is also analysed. We show that narrowest devices appear as the most promising since they operate in fully-depleted regime, even possibly volume inversion.
引用
收藏
页码:65 / 68
页数:4
相关论文
共 10 条
[1]   Layout density analysis of FinFETs [J].
Anil, KG ;
Henson, K ;
Biesemans, S ;
Collaert, N .
ESSDERC 2003: PROCEEDINGS OF THE 33RD EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE, 2003, :139-142
[2]  
Choi Y. K., 2001, IEDM, P421
[3]  
HISAMOTO D, 2001, IEDM, P429
[4]  
Kedzierski J., 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224), p19.5.1, DOI 10.1109/IEDM.2001.979530
[5]   Influence of device engineering on the analog and RF performances of SOI MOSFETs [J].
Kilchytska, V ;
Nève, A ;
Vancaillie, L ;
Levacq, D ;
Adriaensen, A ;
van Meer, H ;
De Meyer, K ;
Raynaud, C ;
Dehan, M ;
Raskin, JP ;
Flandre, D .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2003, 50 (03) :577-588
[6]  
KILCHYTSKA V, 2003, P 11 INT SOI S, V5, P225
[7]   Subthreshold characteristics of p-type triple-gate MOSFETs [J].
Lemme, M ;
Mollenhauer, T ;
Hensche, W ;
Wahlbrink, T ;
Gottlob, H ;
Efavi, J ;
Baus, M ;
Winkler, O ;
Spangenberg, B ;
Kurz, H .
ESSDERC 2003: PROCEEDINGS OF THE 33RD EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE, 2003, :123-126
[8]  
PAUGE F, P ULIS 2003, P27
[9]  
PAVANELLO MA, 2003, P 11 INT SOI S, V5, P261
[10]   MODELING OF TRANSCONDUCTANCE DEGRADATION AND EXTRACTION OF THRESHOLD VOLTAGE IN THIN OXIDE MOSFET [J].
WONG, HS ;
WHITE, MH ;
KRUTSICK, TJ ;
BOOTH, RV .
SOLID-STATE ELECTRONICS, 1987, 30 (09) :953-968