Design of Delay-Locked Loop for Wide Frequency Locking Range

被引：0

作者：

Chen, Hsun-Hsiang ^{[1
]}

Wong, Zih-Hsiang ^{[1
]}

Chen, Shen-Li ^{[2
]}

机构：

[1] Natl Changhua Univ Educ, Dept Elect Engn, 2 Shi Da Rd, Changhua 500, Taiwan

[2] Natl United Univ, Dept Elect Engn, Changhua 500, Taiwan

来源：

2013 INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC) | 2013年

关键词：

DLL; FVC;

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In order to increase the frequency locking range, a delay-locked loop (DLL) circuit with frequency to voltage converter (FVC) and phase select circuit is described. For the low power dissipation consideration, the circuit's bias current is keep at lower level. The simulation results show that the operating frequency range extend from 106 MHz similar to 151 MHz to 54 MHz similar to 250 MHz, and the power dissipation increases from 2.47 mW similar to 3.33 mW to 6.7 mW similar to 14 mW.

引用

页码：302 / 305

页数：4

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