A 20F2/Bit Current-Integration-Based Differential NAND-Structured PUF for Stable and V/T Variation-Tolerant Low-Cost IoT Security

被引:10
作者
Lee, Jongmin [1 ]
Kim, Minsun [1 ]
Jeong, Minhyeok [1 ]
Shin, Gicheol [1 ]
Lee, Yoonmyung [1 ]
机构
[1] Sungkyunkwan Univ, Dept Elect & Comp Engn, Suwon 16419, South Korea
基金
新加坡国家研究基金会;
关键词
Transistors; Costs; Internet of Things; MOSFET; Security; Circuit stability; Inverters; Area-efficient; cost-effective; differential nand; hardware security; Internet of Things (IoT); physically unclonable function (PUF); weak PUF; PHYSICALLY UNCLONABLE FUNCTION; BIT-ERROR; CIRCUIT;
D O I
10.1109/JSSC.2022.3192903
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A current-integration-based differential NAND-structured physically unclonable function (PUF) with 20F(2) area per bit is proposed for low-cost IoT security. Current integration scheme with a capacitor is adopted to generate a response bit by comparing the delay of capacitor charging through pair of selected MOSFET transistors. For area-efficient implementation, minimum-sized MOSFETs are selected from NAND-flash-like array structure. By operating selected MOSFET pairs in moderate inversion mode, higher sensitivity to threshold voltage (V-th) variation, and hence more stable response generation, is achieved while keeping it faster than weak inversion operation. A stabilization scheme based on current integration is proposed by discarding or remapping the transistor pairs that generate small charging delay difference. The proposed current-integration-based differential NAND-structured PUF (CI NAND-PUF) achieved high V/T variation tolerance of 0.145%/ 0.1 V and 0.120%/10 degrees C while limiting 20F(2)/bit area for 1-bit random response generation. With the proposed stabilization scheme, up to 11x and 7.7x BER improvement is achieved for trimming and remapping, respectively.
引用
收藏
页码:2957 / 2968
页数:12
相关论文
共 34 条
[1]   Static Physically Unclonable Functions for Secure Chip Identification With 1.9-5.8% Native Bit Instability at 0.6-1 V and 15 fJ/bit in 65 nm [J].
Alvarez, Anastacia B. ;
Zhao, Wenfeng ;
Alioto, Massimo .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2016, 51 (03) :763-775
[2]  
Bryant T, 2017, 2017 IEEE INTERNATIONAL SYMPOSIUM ON HARDWARE ORIENTED SECURITY AND TRUST (HOST), P140, DOI 10.1109/HST.2017.7951813
[3]  
Choi Y., 2020, IEEE INT SOLID STATE, P16
[4]  
Jeloka S, 2017, SYMP VLSI CIRCUITS, pC270, DOI 10.23919/VLSIC.2017.8008504
[5]   A Physical Unclonable Function With Bit Error Rate < 2.3 $\times$ 10-8 Based on Contact Formation Probability Without Error Correction Code [J].
Jeon, Duhyun ;
Baek, Jong Hak ;
Kim, Yong-Duck ;
Lee, Jaeseong ;
Kim, Dong Kyue ;
Choi, Byong-Deok .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2020, 55 (03) :805-816
[6]  
Karpinskyy B, 2016, ISSCC DIG TECH PAP I, V59, P158, DOI 10.1109/ISSCC.2016.7417955
[7]   Zero bit error rate ID generation circuit using via formation probability in 0.18 μm CMOS process [J].
Kim, T. W. ;
Choi, B. D. ;
Kim, D. K. .
ELECTRONICS LETTERS, 2014, 50 (12) :876-+
[8]  
Lee J., 2021, PROC IEEE ASIAN SOLI, P1
[9]  
Lee J., 2019, PROC IEEE 45 EUR SOL, P1
[10]   A 354F2 Leakage-Based Physically Unclonable Function With Lossless Stabilization Through Remapping for Low-Cost IoT Security [J].
Lee, Jongmin ;
Lee, Donghyeon ;
Lee, Yongmin ;
Lee, Yoonmyung .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2021, 56 (02) :648-657