A low-power phase-locked loop for UWB applications

被引：1

作者：

Rapinoja, Tapio ^{[1
]}

Stadius, Kari ^{[1
]}

Halonen, Kari ^{[1
]}

机构：

[1] Aalto Univ, Elect Circuit Design Lab, POB 3000, Espoo 02015, Finland

来源：

24TH NORCHIP CONFERENCE, PROCEEDINGS | 2006年

关键词：

D O I：

10.1109/NORCHP.2006.329236

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper describes a low-power phase-locked loop (PLL) design for multiband-OFDM UWB synthesizer implemented in a 0.13-mu m CMOS process. Three parallel PLLs and a multiplexer (MUX) constitute a frequency synthesizer which is used to generate carrier frequencies to UWB band groups 1 and 3. The implemented PLL consumes only 10 mW from a 1.2-V supply. Moreover, it achieves a close-in spurious tone level of -54 dBc and in-band phase noise of -78 dBc/Hz.

引用

页码：23 / +

页数：2

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