共 5 条
[1]
[Anonymous], 1970, IBM J RES DEV
[2]
Multiple bit upset tolerant memory using a selective cycle avoidance based SEC-DED-DAEC code
[J].
25TH IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS,
2007,
:349-+
[3]
ERROR DETECTING AND ERROR CORRECTING CODES
[J].
BELL SYSTEM TECHNICAL JOURNAL,
1950, 29 (02)
:147-160