A Floating-point FFT Twiddle Factor Implementation Based on Adaptive Angle Recoding CORDIC

被引：0

作者：

Phuong-Thao Vo-Thi ^{[1
]}

Trong-Thuc Hoang ^{[1
]}

Cong-Kha Pham ^{[2
]}

Duc-Hung Le ^{[1
]}

机构：

[1] Univ Sci Ho Chi Minh City, 227 Nguyen Van Cu St,Dist 5, Ho Chi Minh City, Vietnam

[2] Univ Electrocommun, 1-5-1 Chofugaoka, Tokyo 1828585, Japan

来源：

2017 INTERNATIONAL CONFERENCE ON RECENT ADVANCES IN SIGNAL PROCESSING, TELECOMMUNICATIONS & COMPUTING (SIGTELCOM) | 2017年

关键词：

ALGORITHM; DESIGN; CORE;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper, a single-precision floating-point FFT Twiddle Factor (TF) implementation is proposed. The architecture is based on Adaptive Angle Recoding CORDIC (AARC) algorithm. The TF design is built and verified on Altera Stratix IV FPGA chip and 65 nm SOTB synthesis. The FPGA implementation has 103.9 MHz maximum frequency, throughput result of 16.966 Mega-Sample per second (MSps), and resources utilization of 7, 747 ALUTs and 625 registers. On the other hand, the SOTB synthesis has 16,858 standard cells on an area of 86,718um(2), 166 MHz maximum frequency, and the speed of 27.107 MSps. The accuracy results are 1.133E - 10 Mean-Square-Error (MSE) and about 26 part-per-million (ppm) maximum error-ratio.

引用

页码：21 / 26

页数：6

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