Power analysis for high-speed I/O transmitters

被引：8

作者：

Hatamkhani, H ^{[1
]}

Yang, CKK ^{[1
]}

机构：

[1] Univ Calif Los Angeles, Newport Coast, CA 92657 USA

来源：

2004 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS | 2004年

关键词：

D O I：

10.1109/VLSIC.2004.1346536

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper studies the design tradeoffs to minimize power dissipation of multi-Gbps parallel I/O transmitters. A macromodel of a transmitter that can be optimized for power is presented. Also discussed is a means to consider the impact of deterministic jitter due to on-chip buffering on power dissipation. The model allows analysis that considers varying design constraints, and circuit architectures. The optimization results provide some guidance on the choice of architecture, and data rate to achieve large aggregate I/O bandwidths.

引用

页码：142 / 145

页数：4